On August 19, researchers from SK Hynix, the University of Virginia, MIT, Nanyang Technological University, and other institutions published a review paper in Nature Electronics titled 'Co-packaged optics for high-performance computing and AI,' systematically outlining the development path of CPO in high-performance computing and AI, and proposing a longer-term roadmap: pushing optical interconnects to memory interfaces.
In traditional approaches, data must first travel as electrical signals from the chip to an optical module at the edge of the device before conversion; CPO places optical components directly near the chip, shortening high-speed electrical signal transmission distances, reducing power consumption, and increasing bandwidth. SK Hynix's proposed next step is to continue pushing inward, extending optical links between AI accelerators and memory, forming a 'photonics-centric' system architecture.
In this architecture, compute chips like GPUs can connect to larger memory pools through photonic interposers, allowing multiple AI accelerators to share memory resources, alleviating packaging space and electrical interface constraints, and improving memory resource utilization. The paper's long-term goals include over 100 Tb/s bandwidth per node, below 1 pJ/bit energy consumption, and below 10 nanoseconds inter-chip latency.