This article introduces a new method called 'persistent state machines' that utilizes INT4 in-memory cells for LLM attention, aiming to improve efficiency and reduce memory footprint. This approach could be significant for edge computing and real-time inference.
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An independent research paper proposes using Persistent State Machines (PSM) to execute LLM attention operations in memory cells, claiming dynamic power consumption below 1mW on FPGA, but all energy data are simulation estimates, not physically measured.
The paper proposes a formal discrete framework called 'Persistent State Machines' (PSM) for the attention operator in large language models. The core idea is to broadcast computation to fixed in-memory cells, each performing local deterministic state transitions, thereby avoiding frequent data movement in traditional architectures.
The framework provides complete mathematical proofs, including quantization error bounds, a multi-stage discrete Softmax construction under explicit bounded logits assumptions, deterministic finite automaton equivalence, and space complexity classification as DSPACE(O(n)). These proofs aim to theoretically guarantee the feasibility and numerical stability of the architecture.
For low-power evaluation, the researchers implemented a full 1024-cell array (d=128) on the Xilinx Zynq-7000 xc7z020, using out-of-context (OOC) block design. Post-route functional simulation generated SAIF files, which were annotated to the netlist to estimate the effect of hardware-level self-activated gating.
Results show that the estimated dynamic power of the core logic is below 1.0 mW, with normalized dynamic energy of 3.81×10^-5 pJ/op. This figure suggests that through sparse activation, only a small number of cells produce dynamic switching, significantly reducing power consumption. However, note that these data come from simulation tools, not physical measurements.
To verify system-level compatibility, the researchers integrated a 256-cell subarray (representing an integrated single-head attention system) into a complete SoC, including the AMBA AXI4 interconnect and AMD Xilinx PCIe Gen3 x1 bridge (XDMA v4.2). The entire SoC achieved timing closure in the AWS Cloud FPGA development environment, with a unified system clock of 62.5 MHz and a worst negative slack (WNS) of +1.854 ns.
The SoC occupies only 0.67% of the device's logic slices and 0.00% of DSP blocks, indicating high scalability potential. This result demonstrates that even on resource-constrained FPGAs, the PSM architecture can achieve system integration with minimal area overhead.
Functional simulation used over a thousand random vectors, compared against a fixed-point software reference implementation, achieving bit-exact agreement. This provides strong evidence for the correctness of the architecture, but only at the simulation level.
The paper explicitly states that all energy data are estimates based on simulation tools for synthesized logic, with no physical FPGA board-level measurements, and system-level external memory energy is strictly excluded. Therefore, actual power consumption may be higher than estimated, especially when considering memory access and I/O overhead.
The paper is published as a preprint on Zenodo, version v8, authored by independent researcher Esaka, Yusuke, affiliated with Cosmos Administrative Scrivener Office. The paper also mentions a Japanese patent application (No. 2026-177318), with status 'patent pending'.
It is important to note that this research has not undergone peer review, and the source is a Hacker News AI-filtered repost, making it second-hand reporting. Therefore, the conclusions in the paper should be regarded as author claims, not confirmed facts.
This report is based on the abstract and metadata of a preprint paper, sourced from a Hacker News AI-filtered repost, making it a second-hand source. Key data in the paper (such as power, energy, timing) are estimates by the authors in a simulation environment, not physically verified, and have not undergone peer review. Therefore, these data should be regarded as author claims, not confirmed facts.
Persistent State Machines offer a new in-memory computing approach for LLM attention computation, theoretically capable of significantly reducing power consumption, but current evidence is limited to simulation; actual effectiveness requires physical verification and peer review.
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