NVIDIA is deploying its new Vera CPU to accelerate electronic design automation (EDA) workflows used in developing next-generation CPUs and GPUs. Collaborating with Cadence and Synopsys, early tests show Vera speeding up critical tasks like formal verification and logic simulation. This could shorten chip design cycles and boost the pace of semiconductor innovation.
SynthePulse Insight · AI deep reading
Version 1 · 1 source
NVIDIA is deploying its custom Vera CPU in its own chip design flow, collaborating with Cadence and Synopsys to optimize EDA tools. Early tests show up to 1.5x performance gains on key verification and simulation workloads. This move not only accelerates chip iteration but also creates a closed loop: using NVIDIA CPUs to design NVIDIA CPUs/GPUs.
Although GPUs and AI have accelerated many aspects of chip design, critical EDA workloads such as logic simulation, formal verification, and digital implementation still heavily rely on CPU performance. These tasks require fast single-core speed, efficient memory systems, and high overall throughput. CPU architecture directly determines how quickly engineering teams can verify designs, explore options, and tape out.
The Vera CPU features 88 custom NVIDIA Olympus cores, a power-efficient LPDDR5X memory subsystem, and a second-generation NVIDIA scalable coherence architecture, designed to deliver strong single-core performance, high memory bandwidth, and consistent low latency for engineering applications. These characteristics are especially important for mixed latency-sensitive tasks and large-scale regression testing.
Early tests focused on Cadence Jasper formal verification platform and Synopsys VCS functional verification solution. Under the same core count, selected production workloads showed up to 1.5x performance improvement. NVIDIA is collaborating with both companies on application profiling, software optimization, and system-level tuning to enhance engineering efficiency across broader workflows.
Chip design begins with architecture definition, where engineers describe behavior at the register transfer level (RTL). Then, through logic simulation, formal verification, regression testing, and digital implementation, the design is transformed into manufacturable silicon. These stages are interconnected; improvements in verification throughput help detect issues earlier, reducing downstream design iteration costs.
NVIDIA's deployment of Vera in its own engineering workflow reflects its strategy of choosing the most suitable computing architecture for each workload. In EDA, GPUs and AI continue to accelerate algorithms, while high-performance CPUs remain the cornerstone for critical simulation, verification, and implementation workloads.
Looking ahead, NVIDIA plans to introduce the next-generation Rosa CPU based on Rigel cores and continue optimizing EDA applications. By using NVIDIA CPUs to design future NVIDIA CPUs and GPUs, the company builds a continuous feedback loop among silicon design, software optimization, and systems engineering, where each generation lays the foundation for the next.
This article primarily draws from NVIDIA's official blog, a first-party source. Performance data (1.5x improvement) is based on early tests and limited to 'selected production workloads'; actual deployment results may vary by workload type and system configuration. Collaborations with Cadence and Synopsys, as well as future Rosa CPU plans, are official NVIDIA statements.
NVIDIA's deployment of the Vera CPU in its chip design flow not only validates the competitiveness of its custom CPU in EDA but also creates an accelerated iteration loop through 'self-production and self-use.' Although the 1.5x performance gain is early data, it indicates that CPU architecture optimization remains a key lever for improving chip design efficiency.
Primary report
Primary source