AMD Unveils World's First 2nm GPU MI455X and Helios System, Attracts OpenAI, Meta, Microsoft as Customers

AMD unveiled the Instinct MI455X accelerator and Helios rack system at the Advancing AI event on July 23, 2026. The MI455X uses a chiplet design with four TSMC N2 process compute chiplets (XCD), two N3P process cache and interconnect chiplets (FCD), plus I/O chiplets and 12 HBM4 memory stacks, totaling ~320 billion transistors. Each GPU has 432GB HBM4; a Helios rack integrates 72 GPUs and 18 EPYC Venice CPUs, delivering ~2.9 ExaFLOPS FP4, with 260TB/s intra-rack interconnect bandwidth and 43TB/s external network bandwidth.

Helios uses the OCP open rack specification, with UALink and UALoE internally and Ultra Ethernet Consortium technology externally, combined with AMD Pensando networking chips. AMD positions it as a reference design, with final systems built by OEMs, ODMs, and cloud providers. The sixth-generation EPYC Venice CPU uses Zen 6 architecture, 256 cores, 203 billion transistors, and frequencies above 5GHz; AMD claims it is the first high-performance computing product using TSMC's 2nm process to enter production ramp.

AMD announced customers including OpenAI, Meta, Microsoft, Oracle, and Anthropic. OpenAI signed an up-to-6GW multi-generational agreement in October 2025, with the first 1GW planned for deployment in the second half of 2026 based on the MI450 series; AMD provided up to 160 million share warrants. Meta also signed an up-to-6GW agreement, with the first 1GW delivered from the second half of 2026 using a co-customized MI450 series; AMD also provided up to 160 million share warrants. Oracle plans to deploy 50,000 MI450 series GPUs starting in the third quarter of 2026. Anthropic reached an up-to-2GW strategic partnership, with the first phase of 1GW expected online in the first half of 2027; AMD plans to invest up to $5 billion. Microsoft CEO Satya Nadella said they will use Helios to expand Azure infrastructure.

AMD Vice President Andrew Dieckman stated that CUDA is rarely mentioned in discussions with large customers because enterprises are building on high-level abstractions like PyTorch, vLLM, and Triton; whether the underlying layer is CUDA or ROCm is less visible to developers, calling CUDA a 'non-event.' AMD promises support for PyTorch, TensorFlow, JAX, ONNX Runtime, vLLM, and Triton at MI455X and Helios launch.

However, this assessment is considered overly optimistic. CUDA is not just a programming interface but includes deep capabilities like math libraries, communication libraries, compilers, and debugging tools. High-level frameworks hide CUDA but do not eliminate dependence on underlying capabilities. When dealing with custom operators, mixed precision, cross-node communication, memory management, or performance diagnostics, development teams still need to go deep into the underlying software stack. Therefore, a more accurate understanding is that CUDA is losing its status as the sole entry point, not that its ecosystem is worthless.

First is delivery: 2nm compute chiplets, 3nm interconnect chiplets, HBM4, and advanced packaging must simultaneously meet yield and capacity requirements. Helios is planned to ship by the end of Q3 2026, supporting gigawatt-scale deployment by 2027. Second is system efficiency: theoretical compute, memory, and interconnect bandwidth must translate into actual model throughput and per-token cost; large-scale production environment data will verify MI455X against Nvidia's Rubin. Third is software: whether ROCm can make framework adaptation, operator optimization, and performance diagnosis routine engineering issues determines if customers are willing to migrate core workloads long-term.

Top-tier customers have signed on for a second source, but have not yet proven they will move their most critical workloads from Nvidia's platform. AMD needs to make ROCm also a 'non-issue'—models run directly, performance is predictable, issues are quickly resolved, and migration no longer requires large engineering teams from both sides.