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Alibaba Releases Qwen3.8-Flash-Next Model Weights as Qwen4 Architecture Preview

Alibaba has released the model weights for Qwen3.8-Flash-Next, a preview of the upcoming Qwen4 architecture, for developers to experiment with and evaluate. The model is a multimodal mixture-of-experts (MoE) model with 176B total parameters, activating 6B per token, and features a native 262,144-token context window extensible to 1M with YaRN.

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Qwen3.8-Flash-Next Weights Released: Where the Qwen4 Preview Pushes Long-Context Costs

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Alibaba has released the weights of Qwen3.8-Flash-Next as a preview of the Qwen4 architecture, while NVIDIA simultaneously provides Day 0 support and has completed inference validation on GB300 NVL72. The real question worth asking is not the parameter scale, but whether this GDN+QSA hybrid architecture can push down the attention and KV cache costs of 1M token context—and the speedup numbers currently supporting this judgment all come from vendor self-reports.

  • Alibaba released the Qwen3.8-Flash-Next weights, positioned as a preview of the upcoming Qwen4 architecture for developers to experiment with and evaluate.
  • The model is a multimodal MoE: a 125B-parameter main model, plus a 51B N-gram embedding, with 6B parameters activated per token.
  • Native context is 262,144 tokens, extendable to 1M tokens with YaRN.
  • In the architecture, three out of every four layers use GDN to compress historical context into a fixed-size recurrent state, while one layer uses QSA for full-context exact retrieval.
  • Alibaba's benchmarks claim QSA achieves up to 7.6x speedup in prefill and up to 4.9x speedup in decode versus full attention; at 1M context with a 90% prefix cache hit rate, prefill throughput is 8.6x that of Qwen3.7-Plus.
  • NVIDIA provides best-effort Day 0 support (SGLang, vLLM, TensorRT LLM) and has validated inference on GB300 NVL72.
Open section navigationWhy a Preview Release Deserves a Separate Look

Why a Preview Release Deserves a Separate Look

Alibaba has released the model weights of Qwen3.8-Flash-Next and explicitly positions it as a preview of the upcoming Qwen4 architecture, intended for developers to experiment with and evaluate. This means the weights currently released are not the final product, but an early exposure of the architectural direction: what developers can test now may still differ from the official Qwen4 release in architecture and parameters, and the source does not state how large that difference might be.

NVIDIA took matching action at the same time: providing best-effort Day 0 functional support through SGLang, vLLM, and NVIDIA TensorRT LLM, and completing inference validation on NVIDIA GB300 NVL72. Note the qualifier "best-effort"—this is not a full production-grade guarantee, but a commitment to functional availability on release day.

Putting these two things together, the substance of this release is: open weights on the model side for evaluation, and a workable path on the hardware and inference stack side in parallel. As for the specific license terms, commercial restrictions, and degree of openness of the weight release, the source does not say.

Parameter Structure: 125B Main Model, 51B N-gram Embedding, 6B Activated per Token

Qwen3.8-Flash-Next is a multimodal mixture-of-experts (MoE) model. Its main model has 125B parameters, plus an additional 51B N-gram embedding, with 6B parameters activated per token.

These numbers determine its deployment profile: the total scale is not small, but the per-token activation is very low, a typical sparse-activation design. For the inference side, what really affects memory and compute usage is the activation path, and the existence of the N-gram embedding as a separate component indicates the model does additional processing at the vocabulary or retrieval-style memory level.

The source does not provide the model's actual performance or benchmark scores on target tasks such as agentic coding, so the parameter structure can only indicate design orientation, not be directly converted into a capability conclusion.

The Two Bottlenecks of Long Context, and the Division of Labor Between GDN and QSA

The source states the bottleneck of long-context inference directly: as context grows, attention computation and KV cache memory simultaneously become limiting. Qwen3.8-Flash-Next's response is a hybrid architecture combining Gated DeltaNet (GDN) with Qwen Sparse Attention (QSA).

The division of labor is clear: three out of every four layers use GDN, continuously compressing historical context into a fixed-size recurrent state, thereby eliminating KV cache growth as sequences lengthen; the remaining layer uses QSA to perform exact retrieval across the full context. This is an interleaved layer design of "compression as the main approach, exact retrieval as the auxiliary."

QSA itself targets a pain point of previous sparse attention schemes: they previously relied on token-level indexers, and as context grew longer, the computational overhead of the index itself became increasingly high. QSA instead aggregates sequences into micro-blocks, estimates importance at the block level, and selects only the most relevant regions, thereby reducing attention, computation, and indexing overhead within each layer. The source considers this design particularly suitable for architectures that alternate GDN and QSA.

It is necessary to distinguish clearly: the above is an architectural description, a confirmed fact about the model design; how large the efficiency gains it brings are depends on the vendor benchmark numbers in the next section.

7.6x, 4.9x, 8.6x: The Attribution of These Numbers Must Be Seen Clearly

Alibaba's published benchmarks show that, compared with full attention, the QSA attention kernel achieves up to 7.6x speedup in the prefill stage and up to 4.9x speedup in the decode stage. In another test, under a cache-intensive online serving scenario with 1M token context length and a 90% prefix cache hit rate, Qwen3.8-Flash-Next's prefill throughput reaches 8.6x that of Qwen3.7-Plus.

These numbers must be read according to their source attribution: they are all published by Alibaba and are vendor self-reported benchmark results, not independently reproduced by a third party. The source itself also phrases them as "Alibaba's published benchmarks show" and "Alibaba's released benchmarks indicate," rather than as independently verified conclusions.

Therefore the reasonable reading is: these multiples show that the architecture has significant efficiency potential under specific test conditions, but they cannot be directly extrapolated to actual performance in any deployment environment. Actual deployment performance may differ, and this point is also explicitly listed in the source's constraint notes.

Also note that the condition for the 8.6x figure to hold is quite specific—1M token context, 90% prefix cache hit rate, cache-intensive online serving test. Citing this multiple outside these premises would distort it.

Throughput on GB300 NVL72, and the Gap with Local Hardware

GB300 NVL72 uses a rack-scale architecture, integrating 72 NVIDIA Blackwell Ultra GPUs into a single platform, with its 72-GPU NVLink domain enabling 130 TB/s of all-to-all communication. The source emphasizes that the significance of this bandwidth lies in eliminating the bottleneck when expert traffic crosses traditional networks—for MoE models, the communication overhead of expert routing is precisely a key constraint.

Running Qwen3.8-Flash-Next on this platform, the source gives the performance as over 16K tokens per second per GPU and over 200 tokens per second per user. This data comes from NVIDIA's own blog, is a vendor self-report, and likewise lacks third-party verification.

Beyond rack-scale deployment, the model can also run on local NVIDIA hardware, including NVIDIA DGX Station, NVIDIA DGX Spark clusters, and workstations equipped with four NVIDIA RTX PRO 6000 Blackwell Max-Q workstation-edition GPUs. The usage path given by the source is: prototype and evaluate on local hardware, then scale the same model to GB300 NVL72 for production serving.

However, the actual performance on local hardware is not quantified by the source. Therefore "local prototyping, rack-scale production" is a described pathway, not a performance comparison supported by data.

From Fine-Tuning to Deployment: What Developers Can Actually Get

On post-training, developers can use NVIDIA NeMo AutoModel for fine-tuning, supporting full SFT or the more memory-efficient LoRA; further, they can use NVIDIA NeMo RL recipes for reinforcement learning. The source mentions that this library is PyTorch-native, has Day-0 Hugging Face checkpoint support, and can train directly on existing checkpoints without model conversion.

On the inference side, SGLang, vLLM, and TokenSpeed provide open-source inference recipes for developers to deploy the model on NVIDIA accelerated platforms. On access channels, the model weights can be downloaded from Hugging Face or ModelScope, deployed through the model-free NVIDIA NIM on NVIDIA NGC, or tried directly on QwenCloud.

The model targets high-concurrency, context-intensive applications, and the scenarios listed by the source include agentic coding, document processing, and tool-driven workflows. These are target positioning; the source does not provide actual performance data in these scenarios.

The Boundaries of This Material

This article is entirely based on a single source, the NVIDIA developer blog, and lacks cross-verification from Alibaba's official release notes or other independent sources. The QSA speedup multiples and the 8.6x prefill throughput are both benchmark results published by Alibaba, not independently reproduced by a third party; the GB300 NVL72 throughput data comes from NVIDIA's own blog and is a vendor self-report.

The blog page itself contains an AI summary generated by NVIDIA Nemotron, and the page explicitly warns that AI-generated content may be incomplete and that important information should be verified independently. This constitutes an additional caution for citing the numbers in it.

Matters not yet clarified include: the differences in architecture and parameters between Qwen3.8-Flash-Next and the final official Qwen4 release; the specific license terms, commercial restrictions, and degree of openness of the model weights; and horizontal comparison data between this model and other long-context models of the same period. These gaps mean that the judgment currently available is limited to "the architectural direction and deployment path have been made public," rather than "performance has been independently confirmed."

Credibility boundary

This article is based solely on a single source, the NVIDIA developer blog, and lacks cross-verification from Alibaba's official release notes or independent sources. The efficiency figures in the text, such as 7.6x, 4.9x, and 8.6x, are all benchmark results published by Alibaba, and 16K tokens/s/GPU and 200 tokens/s/user are NVIDIA self-reported data, none of which have been independently reproduced by a third party. NVIDIA provides only "best-effort" Day 0 functional support for this model, not a full production-grade guarantee. The model is a preview of the Qwen4 architecture, and its final form and official release specifications may change. The blog page includes an AI-generated summary, and the original text warns that AI content may be incomplete and that important information should be verified.

Insight takeaway

The highlight of Qwen3.8-Flash-Next is not the 125B figure, but that it uses a layer-wise division of labor—"three layers of GDN compression + one layer of QSA exact retrieval"—to try to simultaneously dissolve attention computation and KV cache growth under long context. However, the 7.6x, 4.9x, and 8.6x figures supporting its efficiency claims all come from Alibaba's self-reported benchmarks, the GB300 NVL72 throughput comes from NVIDIA's self-report, and NVIDIA only promises best-effort Day 0 support. Therefore what can currently be confirmed is that the architectural direction and deployment path have been made public; whether the performance holds still requires independent verification.

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NVIDIA Developer Blog

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